A complete test plan includes testing the logic and all memories. That is, until the boss adds, “Oh, by the way, the DFT guy left the company, so you also get to do the test stuff. Choose any tools ...

In the real world, we are slaves to our environment. The decisions we make are dependent on the resources available at any given time. In school, I remember coming up with a binary decision diagram ...

My colleagues from Mentor Graphics, Ron Press, Martin Keim, and I often write about various aspects of digital IC test. If you started following the Test Voices blog when it was part of Test & ...

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been ...